1. Field of the Invention
The present invention relates to a digital-to-analog ("D/A") converter, used in signal processing and possibly with audio reproduction technology, for converting a digital signal into an analog signal. The DIA converter may additionally relate to a switched-capacitor D/A converter having low power consumption, and may further relate to a delta-sigma D/A converter using the same.
2. Description of the Related Art
In the manufacture of semiconductor integrated circuits, it is generally easier to produce capacitors than other circuit elements such as resistors, diodes, and the like. A switched-capacitor D/A converter is frequently used to perform D/A conversion, wherein the switched-capacitor D/A converter generates a desired analog signal by controlling the sampling and transfer of electric charge. The electric charge is temporarily placed on a plurality of capacitors using a digital signal, wherein the values of those capacitors are generally set at a predetermined capacitance ratio.
FIG. 1 is a circuit diagram of a conventional switched-capacitor D/A converter. The switched-capacitor D/A converter includes an operational amplifier 10. Amplifier 10 is coupled to have a voltage follower function such that an output terminal of the amplifier is connected to an inverting input terminal. The non-inverting input terminal is operably coupled to a plurality of capacitors C1 to Ci. Each of a plurality of switches SW1 to SWi is coupled to opposite ends of corresponding capacitors C1 to Ci. A plurality of switches SWG1 to SWGi are connected selectively to one of two dissimilar reference voltages Vr+ and Vr-, and also to a clock signal supply section 20 for supplying two kinds of clocks +1 and .phi.2.
As shown in FIG. 3, the two kinds of clocks .phi.1 and .phi.2 supplied from the clock supply section 20 each repeat at high and low voltage levels at a predetermined interval. When one of the clocks is at the high level, the other is at the low level, so that the high levels of the two clocks do not overlap.
The switches SW1 to SWi respectively enter a closed state when the clock .phi.1 is at the high level and otherwise enter an open state. The closed state occurs during a high level of clock .phi.1. Furthermore, the switches SWG1 to SWGi are connected to either of two reference voltage sources Vr+ or Vr-, depending on a polarity (+1 or -1) of digital data S1 to Si. Thus, when the clock .phi.2 is at a high level and the polarity of the digital data Si is "+1", the switches SWG1 to SWGi are respectively connected to the reference voltage source Vr+ (shown by labeling "Si.multidot..phi.2"). On the other hand, when the clock .phi.2 is at a high level and the polarity of the digital data Si is "-1", the switches SWG1 to SWGi are respectively connected to the reference voltage source Vr- (shown by labeling "Sib .phi.2"). Hereinafter, the suffix b represents a logical inversion.
The operation of the circuit shown in FIG. 1 depends on the status of the clocking signals .phi.1 and .phi.2. When the clock 41 is at a high level, the switches SW1 to SWi enter a closed state, and opposite (or both) terminals of all the capacitors C1 to Ci are connected to ground. When the clock .phi.2 is at a high level subsequent to (or before) .phi.1 being high, the switches SW1 to SWi enter an open state. At the same time, due to the operation of the switches SWG1 to SWGi, and depending on the polarity (+1 or -1) of the digital data S1 to Si, the left-hand terminals of the capacitors C1 to Ci are connected to the reference voltage source of either Vr+ or Vr-.
As a result, the distribution of electric charges occur among the capacitors, and since the total sum of the charges at a node Va (at a non-inverting input terminal position of the operational amplifier 10) becomes zero according to the law of charge conservation, the following equation (1) is given: EQU Va-Si.multidot.Vr).multidot.Ci+(Va-Si-1.multidot.Vr).multidot.Ci-1+ . . . +(Va-S1.multidot.Vr).multidot.C1=0 (1)
where Vr is the absolute value of Vr+ or the absolute value of Vr-, and Ci is the capacitance of a orresponding capacitor.
In equation (1), if the capacitance values of the capacitors C1 to Ci are in the binary ratio (i.e., Ci=2.multidot.Ci-1, . . . , C2=2-C1), then the following equation (2) will result: EQU (Va-Si.multidot.Vr).multidot.Ci.multidot.2.sup.i-1 +(Va-Si-1.multidot.Vr).multidot.Ci.multidot.2.sup.i-2 + . . . +(Va-S1.multidot.Vr).multidot.C1=0 (2)
Since the output (OUT) of D/A conversion becomes equal to Va due to the follower operation of the operational amplifier 10, the voltage OUT is given by the following equation (3): EQU OUT=Vr.multidot.(Si.multidot.2.sup.i-1 +Si-1.multidot.2.sup.i- + . . . +S1)/(2.sup.i -1) (3)
As explained above, according to equation (3), the switched-capacitor circuit shown in FIG. 1 performs D/A conversion of i number of bits.
Typically, a parasitic capacitance Cp is present at node Va. Parasitic capacitance is inherent in the manufacture and operation of the switching node, and is shown by the dotted line in FIG. 1. Capacitance Cp induces a term "Va.multidot.Cp" at the left side of equation (2), and a D/A conversion error will result. In practice, parasitic capacitance such as an input capacitance of the operational amplifier 10 will certainly exist. In the prior art shown in FIG. 1, the parasitic capacitance Cp adversely affects the operational accuracy of the D/A converter.
Reference documents which describe the switched capacitor D/A converter of this kind include Van de Plassche, "Integrated Analog-to-Digital and Digital-to-Analog Converters", Kiuwer Academic Publishers, 1994, pp. 229; and, Tsividis, "A Segmented u-255 Law PCM voice Encode Utilizing NMOS Technology", IEEE J, Of Solid-State Circuits, Vol. SC-11, pp. 740-747, December. 1976.
In order to solve the problems arising in the circuit of FIG. 1, a switched-capacitor D/A converter as shown in FIG. 2 may be used. The switched-capacitor D/A converter of FIG. 2 includes an operational amplifier 11 having a capacitor Ctot and a switch SA2 connected between an output terminal and an inverting input terminal of the amplifier. A switch SA1 is connected between the capacitors C1 through Ci and the inverting terminal of the operational amplifier 11. A plurality of switches SR1 through SRi are connected to opposite ends of corresponding capacitors C1 to Ci, and a plurality of switches SRG1 to SRGi are each connected to one of two kinds of reference voltage sources Vr+ and Vr-. A clock supply section 21 is used for supplying two kinds of clocks .phi.1 and .phi.2.
Clocks .phi.1 and .phi.2 supplied from the clock supply section 21 do not differ from those supplied from the clock supply section 20 shown in FIG. 1. Each of the switches SR1 through SRi includes a subswitch (labeled .phi.1) which is connected to a right-hand terminal of the corresponding one of capacitors C1 through Ci. Subswitch .phi.1 enters a closed state when clock .phi.1 is at a high level, and otherwise remains open. Switches SR1 and SRi also include a subswitch (labeled .phi.2) which is connected to a left-hand terminal of the corresponding one of the capacitors C1 to Ci. Subswitch .phi.2 enters a closed state when clock .phi.2 is at a high level, and otherwise remains open.
The switches SRG1 to SRGi are respectively connected to one of the reference voltage sources Vr+ and Vr- depending an the polarity (+1 or -1) of digital data Si. When the clock .phi.1 is at a high level and the polarity of digital data Si is "+1", a respective switch SRGi is connected to the voltage source Vr+ (this situation is indicated by labeling Si.multidot..phi.1). Conversely, when the lock .phi.1 is at the high level and the polarity of digital data Si is "-1", switch SRGi is connected to the voltage source Vr- (this situation is indicated by labeling Sib.multidot..phi.1).
Switches SA1 and SA2 enter a closed state when the clocks .phi.2 and .phi.1, respectively, are at a high level, and otherwise enter an open state. During operation of the circuit in FIG. 2, when the clock .phi.1 is at the high level, switch SA2 and the right-hand subswitches of switches SR1 to SRi enter the closed state, and the right-hand terminals of all the capacitors C1 to Ci are connected to ground. Furthermore, due to the operation of the switches SRG1 to SRGi, the left-hand terminal of the capacitors C1 to Ci are connected to the reference voltage source Vr+ or Vr- depending an the polarity (+1 or -1) of digital data Si through S1. An electric charge is stored (or "sampled") on the capacitors C1 to Ci in accordance with the reference voltage source.
During closure of switch SA2 the output terminal (OUT) and the inverting input terminal of the operational amplifier 11 are short-circuited. Shorting the input and output terminals causes the electric charge on the feedback capacitor Ctot to becomes zero. Next, when the clock .phi.2 traverses to a high level, the left-hand terminals of the capacitors C1 to Ci connect to ground. At the same time, switch SA1 enters the closed state and the right-hand terminals of capacitors C2 to Ci connect to the inverting terminal of operational amplifier 11.
The inverting terminal of the operational amplifier 11 is in a virtually grounded condition. Due to the negative feedback operation of the operational amplifier 11, once clock .phi.1 traverses to a high level, the electric charge stored on capacitors C1 through Ci are transferred to the capacitor Ctot. This operation results in the following equation (4): EQU Vr.multidot.(Si.multidot.Ci+Si-1.multidot.Ci-1+ . . . +S1.multidot.C1)=OUT.multidot.Ctot (4)
In equation (4), if the capacitance values of capacitors C1 to Ci are in a binary ratio, and also if Ctot=Ci.multidot.(2.sup.i -1), the following equation (5) is introduced: EQU Vr.multidot.(Si-Ci.multidot.2.sup.i-1 +Si-1.multidot.Ci.multidot.2.sup.i-2 + . . . + S1.multidot.C1)=OUT.multidot.Ci.multidot.(2.sup.i -1)(5)
Furthermore, from equation (5), the following equation (6) results: EQU OUT=Vr.multidot.(Si.multidot.2.sup.i-1 +Si-1.multidot.2.sup.i-2 + . . . + S1)/(2.sup.i -1) (6)
As described in equation (6), it will be seen that the switched-capacitor circuit shown in FIG. 2 performs a D/A conversion function of i bits. However, since the inverting input terminal is always in the virtually grounded condition, the charge stored in the parasitic capacitor when .phi.1 is at the high level is equal to that stored in the parasitic capacitor when .phi.2 is at the high level. The overall result is there is no parasitic capacitance added to the inverting input.
Equation (5) is true, however, only in instances of an ideal capacitance ratio. However, it is difficult to manufacture capacitors having an ideal value or capacitors with an ideal capacitance ratio. As a result, the relative inaccuracy (e.g., mismatch of the capacitance ratio) will cause a D/A conversion error. It is further known that in semiconductor circuits, the relative inaccuracy of the capacitance ratio is inversely proportional to the square root of the capacitance value. The greater the capacitance value, therefore, the smaller becomes the mismatch and the D/A conversion error.
In the switched-capacitor D/A converter shown in FIG. 2, the charges stored in capacitors C1 through Ci are transferred to the capacitor Ctot through the virtually grounded input of amplifier 11. More specifically, the charge on capacitors C1 to Ci must be transferred in substantial entirely to Ctot while ensuring the inverting input of amplifier 11 remains at ground. This assumes a substantial amount of time is needed to perform the transfer and, more specifically, for amplifier 11 to supply the transferred charge to Ctot. Accordingly, if the capacitance of capacitor Ctot is increased in order to reduce the D/A conversion error, the amount of charge to be supplied by the operational amplifier 11 will be increased. Since the current and/or power consumption of the operational 11 is determined by this electric charge to be supplied, it is difficult to realize a D/A converter (such as that shown in FIG. 2) having low power consumption and satisfactory accuracy.
Reference documents depicting the preceding arrangements include, for example, U.S. Pat. Nos. 5,162,801; 5,008,674; 4,616,212; and 4,384,277, as well as Gregorian et. al., "Switched-Capacitor Circuit Design", Proc. IEEE, Vol. 71, pp. 941-966, August. 1983.
Turning to FIG. 4, a conventional low power consumption, delta-sigma D/A converter is shown. The converter of FIG. 4 includes a digital interpolation filter 400, a digital delta-sigma modulator 410, a dynamic element matching 420, a current mode D/A converter 430, and an adder 440 capable of adding "dither" thereto.
When 18 bit data, at an Fs rate (sampling rate FS is normally 44.1 kHz) is input as the digital input signal (Din), interpolation is carried out so that a digital signal at an Fos rate (oversampling rate Fos is normally at about 64 fs) is output absent the occurrence of aliasing. Next, the 18 bit data at the Fos rate is subjected to noise-shaping by the digital delta-sigma modulator 410 and is quantized into data having a higher frequency than the sampling rate, as well as a lower resolution (about 4 bits). If the digital interpolation filter 400 and the delta-sigma modulator 410 are ideally manufactured, it will be only necessary to convert the quantized signal into an analog signal by a 4-bit D/A converter. However, since it nearly impossible to maintain the accuracy of 18 bits due to mismatch caused during manufacture of the analog elements, noise is generated due to a D/A conversion error.
For this reason, it is necessary to perform digital processing in order to shift the noise generated by the mismatch of the analog elements to an area outside the pass band of the original digital input which is usually DC to 20 kHz. This will improve the signal-to-noise ratio ("S/N ratio") within the passband. A processing section which performs such digital processing is called dynamic element matching ("DEM"). Data output from the DEM is converted into an analog signal by a 4-bit D/A converter provided at the last stage. In the example shown in FIG. 4, the output data from DEM 420 is fed to the current mode D/A converter 430. The structure of conventional DEM units are well known. For sake of brevity and so as not to detract from a better understanding of the present disclosure, explanation of DEM and the principles behind DEM is unnecessary.
In order to achieve lower power consumption, current mode D/A converter 430 has been implemented with a 4-bit D/A converter using resistors and/or current sources and avoids an operational amplifier. The mismatch of circuit elements such as resistors which construct the current mode D/A converter 430 is potentially as large as 10 times the mismatch of capacitors which occupy about the same area.
DEM 420 controls the current mode D/A converter 430 connected at the later stage by a periodic control sequence. When the mismatch of the circuit elements is large, the periodic control sequence will generate undesirable tones in the analog signal. Here, the periodic control sequence means, for example, when the current mode D/A converter 430 is provided with a plurality of segments which are combinations of current sources and or resistors. Each segment is used with predetermined periodic sequence in order to use all the segments uniformly.
As described above, although power consumption may be reduced in a conventional delta-sigma D/A converter, the S/N ratio will deteriorate as a result of the tones. In order to reduce the tones, it is proposed to add dither to the output of the delta-sigma modulator 410. Dither is a essentially quasi-random signal such as an maximum period sequence signal which is added via adder 440 so that the signal having the periodicity is randomized.
Since addition of dither is equivalent to adding noise, a problem arises in that although the tone is eliminated, the S/N ratio will be deteriorated. Also, addition of dither will increase the manufacturing cost. Thus, a conventional delta-sigma D/A converter employing the current mode D/A converter may fail to achieve both low power consumption and high S/N ratio.
Reference documents related to the above-mentioned delta sigma D/A converters include: Baird et. al., "Linearity Enhancement of Multi-Bit Delta-Sigma A/D and D/A Converters Using Data Weighted Averaging", IEEE Trans. On Cir. and Sys., 11 Vol. 42, No.12, pp. 753-762. December. 1995; and, Hamasaki et. al., "A 3 V, 22 mW Multi-Bit Current Mode Delta Sigma DAC with 100 dB Dynamic Range", IEEE Jr. of Solid-State Circuits, Vol. 31., No.12, pp. 1888-1894, December. 1996.
As set forth above, and shown in FIG. 1, D/A conversion error becomes large due to the influence of the parasitic capacitance. Even if the effect of parasitic capacitance can be eliminated as taught in FIG. 2, unacceptably large power or current consumption may result.
The circuit shown in FIG. 4 is proposed to solve the above-mentioned problems. However, the addition of dither increases manufacturing costs and is equivalent to the addition of noise. Thus, even though tones are eliminated, S/N ratio suffers.
A further problem remains in that the current mode D/A converter, which constitutes the delta-sigma D/A converter, is generally sensitive to jitter of the control clock.